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Esaki Diode-Transistor Memory

IP.com Disclosure Number: IPCOM000097487D
Original Publication Date: 1962-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 60K

Publishing Venue

IBM

Related People

Neff, GW: AUTHOR

Abstract

An Esaki diode transistor pair is used as a basic storage element in a matrix memory. Drawing A is a block diagram of a two by two register organized vertically by words and horizontally by bits. All the bits in one word have a common Word Clear and Select Driver. This has a dual function, namely (1) to clear a word in the register and (2) to provide each bit in that word with a half select input. At the initiation of each write cycle, the word in memory to be altered is cleared and selected by triggering the appropriate Word Clear and Select Driver. Corresponding bits of each word in memory have a common Bit Driver. This is capable of supplying a half select input to all the same order bits of different words in the memory matrix.

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Esaki Diode-Transistor Memory

An Esaki diode transistor pair is used as a basic storage element in a matrix memory. Drawing A is a block diagram of a two by two register organized vertically by words and horizontally by bits. All the bits in one word have a common Word Clear and Select Driver. This has a dual function, namely (1) to clear a word in the register and (2) to provide each bit in that word with a half select input. At the initiation of each write cycle, the word in memory to be altered is cleared and selected by triggering the appropriate Word Clear and Select Driver. Corresponding bits of each word in memory have a common Bit Driver. This is capable of supplying a half select input to all the same order bits of different words in the memory matrix. The word to be read into memory is brought in parallel to the bit drivers and is read into that word which was cleared and half selected. Similarly, all bits of each word have a common read gate so that all bits in a given word are read out on their respective output lines.

Drawing B shows a particular Esaki diode-transistor combination of each memory bit. Esaki diode E is biased for bistable operation through source I(DC) and provides a bias to the base of an NPN transistor T. This is when diode E is in its high voltage stable state. Transistor T does not conduct since its emitter e is not properly energized. Readout of Bit 1 is provided by a negative pulse P applied to the read gate terminal. If Esaki diode E is in its 1 state, a readout signal is obtained across R(L). If it is in its low voltage stable state, 0 state, transistor T is not biased to conduct and a negative pulse P at its corresponding read gate terminal does not produce an output signal. The base current drawn by transistor T can be made small...