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Bidirectional Counter

IP.com Disclosure Number: IPCOM000097509D
Original Publication Date: 1961-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Rosenberg, LJ: AUTHOR

Abstract

Three stages of a binary coded decimal counter are shown. Pulses applied on the count down pulse line cause the contents of the counter to be reduced. Pulses applied on the count up pulse line cause the contents of the counter to be increased.

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Bidirectional Counter

Three stages of a binary coded decimal counter are shown. Pulses applied on the count down pulse line cause the contents of the counter to be reduced. Pulses applied on the count up pulse line cause the contents of the counter to be increased.

A negative going pulse at the reset R input of a trigger T turns it OFF, the 0 output assuming a positive state and the 1 output assuming a negative state. A negative going pulse at the complement C input causes a reversal in whatever state exists. The output of an AND +A is negative when all inputs are positive. The output of a Minus OR -0 is negative when any input is negative.

When counting up, the -V pulse on the count up pulse line causes the first trigger (weight 1) to be set ON. The second -V pulse causes the first trigger to go OFF, while the second trigger (weight 2) comes ON due to the negative transition originating in the associated series connected AND and OR circuits. The OR circuits and the left hand AND circuits are utilized for all further counting up in like manner.

When counting down, the OR circuits and the right hand AND circuits are used. A +V pulse applied on the count down pulse line (assuming triggers of weight 2 and 4 are ON) causes the middle trigger to be reset OFF through the associated AND circuit, and the bottom trigger to be complemented ON through the bottom OR circuit. Thus, the count changes from six to five. Further counting down continues in like manner.

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