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Switching Circuit

IP.com Disclosure Number: IPCOM000097511D
Original Publication Date: 1961-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Moyer, JJ: AUTHOR

Abstract

The high speed switching circuit checks parity. Each OR gate 10... 13 produces an output signal which is a function of a unique pair of input signals representing the sense of a pair of binary digits in a register. There are also four AND's 14... 17 each having two D. C. signal inputs derived from the OR gates and a pulse input.

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Switching Circuit

The high speed switching circuit checks parity. Each OR gate 10... 13 produces an output signal which is a function of a unique pair of input signals representing the sense of a pair of binary digits in a register. There are also four AND's 14... 17 each having two D. C. signal inputs derived from the OR gates and a pulse input.

AND's sections 15 and 17 are conditioned by OR gates 12 and 13 to respond to bar XY + bar XY. AND's 14 and 16 are conditioned by OR gates 10 and 11 to respond to bar XY + bar XY where X, Y represent binary 1's and bar X, bar Y represent binary 0's. Of the two AND's that are conditioned, one is sensed by a pulse according to the parity of the lower ordered register stages. In this way, the pulse is passed on to a selected one of two output lines 18 and 19.

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