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Sensing Circuit for Bistable Device

IP.com Disclosure Number: IPCOM000097530D
Original Publication Date: 1961-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Lumpkin, C: AUTHOR

Abstract

The circuit is a binary storage device which can be set to either a 1 or 0 state. The state of the device is determined by interrogating one of three input lines, SENSE, SENSE AND SET, or SENSE AND RESET. Initially, a 1 is stored by applying a positive pulse to the set input terminal 10, causing transistor T1 to conduct. Reset winding R resets core 1 and sets cores 2 and 4to their respective 1 states. Also core 5 is inhibited through inhibit winding IW. Thus, the device is set to 1 without producing an output at output terminal 22. The 0 state of the device exists when cores 2 and 4 are in 0 states and cores 1 and 3 are in 1 states.

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Sensing Circuit for Bistable Device

The circuit is a binary storage device which can be set to either a 1 or 0 state. The state of the device is determined by interrogating one of three input lines, SENSE, SENSE AND SET, or SENSE AND RESET. Initially, a 1 is stored by applying a positive pulse to the set input terminal 10, causing transistor T1 to conduct. Reset winding R resets core 1 and sets cores 2 and 4to their respective 1 states. Also core 5 is inhibited through inhibit winding IW. Thus, the device is set to 1 without producing an output at output terminal 22. The 0 state of the device exists when cores 2 and 4 are in 0 states and cores 1 and 3 are in 1 states.

1. Positive Pulse on the SENSE input: Core 2 is reset, causing a pulse on the TR 15. This pulse causes T6 to conduct and current flows in 19 which sets core 5 causing a pulse on the OUTPUT 22. A second winding TW on core 5 causes an output pulse 21 which is delayed. 33 milliseconds. This delayed pulse 21 causes T8 to conduct. The output 20 of T8 resets core 5 and sets cores 1, 2 and 4. The sense input therefore is used to sense the device for a 1 condition without destroying the stored information.

2. Positive Pulse on the SENSE AND SET input: T5 conducts so as to set core 4. Since core 4 is already set, no change occurs and there is no output from the device. The SENSE AND SET input is used to sense for a 0 in the device, but since there is a 1 stored in it there is no output when line 18 is pulsed.

3. Positive Pulse on the SENSE AND RESET input: T2 conducts to reset cores 2 and 4 and set core 3. As core 2 switches, a pulse is produced on TR 15; T6 conducts and sets core 5. A pulse occurs on the OUTPUT 22. The second winding TW on core 5 gives an o...