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Charge Transfer Logic

IP.com Disclosure Number: IPCOM000097532D
Original Publication Date: 1961-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Landauer, RW: AUTHOR

Abstract

The transfer circuit includes three registers A, B and C, each including four ferroelectric capacitors 10... 16, 20...26 and 30... 36. These are selectively polarized in opposite directions, as indicated by the arrows, to represent binary information. Consider that a 1 has been entered into 10 at a time when each capacitor in the A and B registers is at 0. To transfer the information from the C register to A register a positive potential is applied at the C terminal and a negative potential at the A terminal.

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Charge Transfer Logic

The transfer circuit includes three registers A, B and C, each including four ferroelectric capacitors 10... 16, 20...26 and 30... 36. These are selectively polarized in opposite directions, as indicated by the arrows, to represent binary information. Consider that a 1 has been entered into 10 at a time when each capacitor in the A and B registers is at 0. To transfer the information from the C register to A register a positive potential is applied at the C terminal and a negative potential at the A terminal.

Since 10 and 12 are at this time polarized in the same direction in the series circuit extending between terminals A and C, both of these capacitors are switched by the applied voltage as long as a further control transfer capacitor 13 is also similarly polarized. Capacitor 13 and capacitors 15, 23 and 25 allow transfer of information only in a clockwise direction from register C to register A to B and then back to C. Prior to the transfer from C to A, 13 is polarized, by applying a potential to the two terminals shown, in the direction of the arrow T to allow 12, 13 and 20 to have their polarization reversed when the signals are applied coincidently to terminals C and A. The 1 thus transferred to 20 can be transferred to 30 in register B by applying a positive voltage at A and a negative voltage at B after 23 has been polarized in the same direction as these two capacitors. The 1 thus transferred to 30 is transferred back to 12 of register C by applying a positive potential at B and a negative potential at C.

At this time 15 and 13 prevent any back transfer to 10 in register C. When there is a 0 in the capacitor from which transfer is to be made, the two capacitors in the series transfer circuit between the energized terminals are polarized in opposite directions so that neither can be switched. During each transfer the terminal of the register not involved is left floating. Only the transfer lines for the first two capacitors in each group are shown in the figure in order to avoid overcomplicating the drawing.

In the AND-OR circuit, information is transferred from the capacitors 10 and 12 to 20 in accordance with the AND logical function and to 22 in accordance with the OR logical function. Capacitor 20A is added to the circuit as well as a connection 11 betwe...