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Browse Prior Art Database

Binary Multiplier

IP.com Disclosure Number: IPCOM000097535D
Original Publication Date: 1961-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Sanborn, JL: AUTHOR

Abstract

The circuit is capable of performing binary multiplication with a three bit multiplier and three bit multiplicand. The product is formed by combining shift registers and a three-bit parallel adder all of which use cryotrons as switching elements.

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Binary Multiplier

The circuit is capable of performing binary multiplication with a three bit multiplier and three bit multiplicand. The product is formed by combining shift registers and a three-bit parallel adder all of which use cryotrons as switching elements.

The three bit multiplicand is entered in the register formed by MC1, MC2 and MC3. If a multiplicand 101 is entered, the gates of cryotrons 10, 12 and 14 are driven resistive and current flows in paths 16, 18 and 19. The multiplier is entered in the register formed by MP3, MP2 and MP1 to drive appropriate ones of the cryotrons 20... 30 resistive so that the least significant bit of all registers is
1. At the same time or previously the reset line is energized to reset three positions of the partial product register formed by P1... P6. The multiplication is then carried out by alternately energizing the compute and shift lines.

When the compute line is first energized the three-bit multiplicand is read into the adder under the control of the multiplier digit in MP1. If the multiplier bit is 0, all 0's are entered and if 1, the multiplicand is entered as is. The value in the adder is transferred to positions P6, P5, P4 and P3 of the partial product register. The compute pulse also shifts the other two multiplier bits into intermediate stages of the multiplier shift register. The first shift pulse shifts the value in the partial product and multiplier registers one position to the right.

The next compute pu...