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Message Check Character for Serial Transmission System

IP.com Disclosure Number: IPCOM000097546D
Original Publication Date: 1961-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Rumble, DH: AUTHOR

Abstract

A check character is developed from the data characters of a message. It depends upon the relationship between each character and its predecessor. It also cumulatively represents the number of times that bit positions remain one and the number of times that bit positions remain zero in successive message characters.

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Message Check Character for Serial Transmission System

A check character is developed from the data characters of a message. It depends upon the relationship between each character and its predecessor. It also cumulatively represents the number of times that bit positions remain one and the number of times that bit positions remain zero in successive message characters.

The message characters each of which has six bit positions, are successively transferred into shift register SR, upper left drawing, for bit by bit transmission over output 1. Before the bits of a particular character are shifted out onto output 1, the bits are sampled in a gating network 2. This results in a setup of the bits in character register 3 so that the changes in status of the bits between successive characters are determined. Each bit position is sampled in a sequential manner, lower drawing. No sampling or counting is performed for the first character of a message since the relationship between the first character and the initial all-zero reset condition is immaterial.

Assuming that a first character has been entered into register 3, upper left drawing, the subsequent entry of the second character into SR determines whether or not a count is entered into the 1 counter or the 0 counter. This is according to the changes in status encountered among the various bit positions. An individual bit position in 3 is shown in detail in the lower drawing where a flip flop 4 stores the bits in a particular bit position.

The flip flop 4, in conjunction with a sample pulse on line 5, and a bit signal on line 6 from a succeeding character, determines whether the 1 counter, or the 0 counter, or neither counter is actuated. If flip flop 4 is storing a 1 bit from a preceding character, line 7 is at a higher potential level. If 4 is storing a 0 bit from the preceding character, line 8 is at a higher potential level. A 1 bit on the line 6, through AND 9, steps the 1 counter from line 11 through AND 10, if 4 previously had a 1 bit. On the other hand, a 1 b...