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Carry Look Ahead Adder

IP.com Disclosure Number: IPCOM000097547D
Original Publication Date: 1961-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Earle, J: AUTHOR [+2]

Abstract

NOR blocks 1... 3 generate a carry look-ahead signal over two full adder circuits. The first full adder operates on the binary digits A(1) and B(1) and carry in Ci(in) from the previous bit position. The second full adder operates upon the binary digits A(2) and B(2) and the carry C(1) from the first full adder. Each full adder provides a SUM output signal. NOR blocks 1... 20 perform the logic of the STROKE function NOR block, each providing an output when any of the input signals applied to them is absent. The output signal from each NOR block 1...20 is described by the Boolean expressions shown.

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Carry Look Ahead Adder

NOR blocks 1... 3 generate a carry look-ahead signal over two full adder circuits. The first full adder operates on the binary digits A(1) and B(1) and carry in Ci(in) from the previous bit position. The second full adder operates upon the binary digits A(2) and B(2) and the carry C(1) from the first full adder. Each full adder provides a SUM output signal. NOR blocks 1... 20 perform the logic of the STROKE function NOR block, each providing an output when any of the input signals applied to them is absent. The output signal from each NOR block 1...20 is described by the Boolean expressions shown.

The inputs to NOR blocks 1...3 are selected so that the carry out C(out) signal is generated for the combination of the first and second full adders plus the carry in C(in) from the previous bit position.

The same circuit performs successfully when the NOR blocks 1...20 perform the logic of the DAGGER function NOR block, each providing an output signal only when all of the input signals applied to them are absent. The DAGGER function implementation of this circuit requires that the complement of the input signals shown be applied to the circuit. The complement of the output signals shown is provided.

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