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Combined Latch Trigger Circuit

IP.com Disclosure Number: IPCOM000097549D
Original Publication Date: 1961-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Pitkowsky, S: AUTHOR

Abstract

This circuit stores an input signal in a trigger at any time except during a sampling interval when the state of the trigger is latched. A randomly timed signal on line 1 is applied as an input to an OR gate 2 to raise the voltage on an output lead 3 and lower it on lead 4. Lead 3 is one input of AND gate 5 which has a normally positive signal on its other input lead 6 and passes the signal on lead 3 to the output line 7 connected to line 1 to maintain a positive signal on the line to hold gates 2 and 5 conducting.

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Combined Latch Trigger Circuit

This circuit stores an input signal in a trigger at any time except during a sampling interval when the state of the trigger is latched. A randomly timed signal on line 1 is applied as an input to an OR gate 2 to raise the voltage on an output lead 3 and lower it on lead 4. Lead 3 is one input of AND gate 5 which has a normally positive signal on its other input lead 6 and passes the signal on lead 3 to the output line 7 connected to line 1 to maintain a positive signal on the line to hold gates 2 and 5 conducting.

To latch the state of gates 2 and 5 during a sampling period, a third level AND gate 8 is connected to OR gate 2. Gate 8 normally has both outputs at their lower voltage. During a sampling pulse on clock line 9, output 10 rises if lead 4, the other input to gate 8, is at a high level and output 11 rises if lead 4 is at a low level. Output 10 is connected to a swinging input of OR gate 2 to prevent the gate passing a signal on line 1 if the gate is off and output 11 is connected back to line 1 to hold gate 2 on if it was already conducting.

A third AND gate 12 provides an output signal on line 13 under control of a signal B on line 14 when gate 2 is conducting during the sampling time when the voltage of line 9 is raised.

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