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NAND Logic Clock

IP.com Disclosure Number: IPCOM000097551D
Original Publication Date: 1961-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Zentgraf, HJ: AUTHOR

Abstract

This clock circuit provides sequential outputs 1 through 8 using four latch circuits with a connection arrangement different from the 6position clock described on page 21, this issue of the IBM Technical Disclosure Bulletin.

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NAND Logic Clock

This clock circuit provides sequential outputs 1 through 8 using four latch circuits with a connection arrangement different from the 6position clock described on page 21, this issue of the IBM Technical Disclosure Bulletin.

A pair of NAND gates is associated with each latch and these gates provide the counter outputs. Terminals with like letter notations are connected together.

Each NAND gate has a respective sequence of connections involving an output associated with a particular latch and inputs respectively connected to adjacent latches. This logical sequencing may be used for a ring with even numbers of outputs that number six or greater. Opposite phased input pulses P and bar P are applied to alternate pairs of gates rather than to opposite gates in a pair as is done in the 6position clock.

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