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Browse Prior Art Database

Electronic Commutator

IP.com Disclosure Number: IPCOM000097552D
Original Publication Date: 1961-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Floros, TG: AUTHOR [+2]

Abstract

The clock circuit obtains sequential but separate outputs that number up to twice the number of trigger circuits T used.

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Electronic Commutator

The clock circuit obtains sequential but separate outputs that number up to twice the number of trigger circuits T used.

The outputs are alternately provided by AND gates A-1 through A-16. Some outputs may be skipped if required. The circuit permits direct coupling between component parts.

Input stepping pulses P and bar P are applied to sequentially provide pulses at outputs designated as 1 time through 16 time. These outputs are taken from AND logical blocks of a type that produce complimentary outputs in accord with gating conditions at their inputs, established by the outputs of triggers T-1 through T-8.

Initially, T-1 through T-7 are reset rendering their designated F outputs positive. T-8 is set which renders its bar F output positive. Thus, the positive shift of the first bar P at the input to A-1 produces a negative pulse at its bar G output for 1 time. The positive shift of the G output of A-1 sets T-1 such that its F output now conditions A-2. Further, the F output of T-2 also conditions A-2. The positive shift of the P pulse coincidentally with the negative shift of the aforementioned bar P pulse is thus gated to provide a negative pulse at the bar G output of A-2.

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