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Counter Circuit

IP.com Disclosure Number: IPCOM000097601D
Original Publication Date: 1961-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Riley, WB: AUTHOR

Abstract

The counter uses N number of trigger circuits to obtain 2/N/ number of sequential outputs on separate leads.

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Counter Circuit

The counter uses N number of trigger circuits to obtain 2/N/ number of sequential outputs on separate leads.

In the top drawing 2/N/ number of output AND gates A1... A4 have outputs fed back through delay circuits D1... D4 to the respective inputs of 2/N/ number of input AND gates. Initially, triggers T1 and T2 are reset with the 1 sides conditioning the output AND circuit A1 to provide output 0. Hence, this output conditions first input AND A1. The first input pulse passes A(1) and O(1) to trigger T(1). This lowers output 0 and brings up output 1, which is delayed before conditioning input A(2) to pass the next input pulse. The next input pulse triggers T(1) and T(2) and lowers output 1 and brings up output 2. Similarly, the next input pulse brings up output 3, after which the output pulse sequence is repeated. Binary circuit outputs can be taken from the 0 sides of the triggers. The delay circuits D1... D4 prevent the feed-back of an output pulse before the corresponding input pulse has finished.

The bottom drawing provides the same outputs as the first circuit without delay circuits and with only one-half the AND gates. Complementary pulsed inputs P and P are provided as inputs to alternate gates A1... A4. Initially, triggers T(1) and T(2) are reset with outputs 0 of T(1) and 1 of T(2) up. The first P input pulse passes gate A1 which is conditioned by the 1 output of T(2) to provide circuit output 0. The following P input pulse is applied to A(...