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Error Check of Mode Encoder

IP.com Disclosure Number: IPCOM000097606D
Original Publication Date: 1961-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Rae, A: AUTHOR

Abstract

The circuitry provides an error indication whenever an input pulse entering one of the flip flops A through D results in the issuance of an improperly coded output command pulse. This originates in a pair of NOT AND circuits labeled right dual and left dual. The Truth Table shows the outputs corresponding to the four possible inputs.

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Error Check of Mode Encoder

The circuitry provides an error indication whenever an input pulse entering one of the flip flops A through D results in the issuance of an improperly coded output command pulse. This originates in a pair of NOT AND circuits labeled right dual and left dual. The Truth Table shows the outputs corresponding to the four possible inputs.

An error alarm is generated whenever: (1) there is none or more than one output from the flip flops A through D and (2) whenever there is an output from the NOT AND circuitry that is inconsistent with the Truth Table. When a malfunction in one of the flip flops A through D results in no 1 output, the alarm on the far right is actuated by ANDing the flip flop input pulse with the zero output from the flip flops A through D through the mode check flip flop and the lower row of DDG1 pulse gates.

All other possible errors are detected by ANDing the 1 output of flip flops A through D and the output of the two NOT AND circuits through the upper row of pulse gates DDG1 and the pulse gates DDG3. Any condition not consistent with the Truth Table, either by virtue of a malfunction of one or more of the flip flops A through D, or through a malfunction of the NOT AND circuitry, or through malfunctions of both, results in the impulsing of one or more of the alarms tied to the pulse gates DDG3.

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