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Selective Pulse Control System

IP.com Disclosure Number: IPCOM000097607D
Original Publication Date: 1961-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Pitkowsky, SH: AUTHOR [+2]

Abstract

In some instance the time interval between the end of a required operation time and the next clock pulse which samples the result into the succeeding operation is greater than one-half of a clock cycle. Appreciable time is saved by selecting the opposite phase of the clock for sampling the results and starting the next operation. Thus, if a given data path requires 2 1/4 clock cycles, the outputs are sampled at the 2 1/2 cycle point by gating in the opposite phase of the clock.

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Selective Pulse Control System

In some instance the time interval between the end of a required operation time and the next clock pulse which samples the result into the succeeding operation is greater than one-half of a clock cycle. Appreciable time is saved by selecting the opposite phase of the clock for sampling the results and starting the next operation. Thus, if a given data path requires 2 1/4 clock cycles, the outputs are sampled at the 2 1/2 cycle point by gating in the opposite phase of the clock.

The basic oscillator output on line 1 and its complement on line 2 are applied as inputs to AND's 3 and 4. The outputs of 3 and 4 are combined in OR 5 whose output line 6 is distributed as the controlled clock signal. A trigger 7 has its OFF output 8 connected through delays 9 and 10 to inputs of AND 4 to gate the out- of-phase output line 2 to OR 5. The ON output 11 is connected through delays 12 and 13 to the inputs of AND 3 to enable the line 1 pulses to pass to OR 5. Trigger 7 is set and reset by a pair of latches 14 and 15 respectively controlled by selected turn on and turn off conditions in the clock pulse using device. A clock pulse on line 6 after passing through a delay 16 prevents setting of 14 and 15 at an improper time. It also acts with a previously latched signal in AND's 17 and 18 to pass a change state signal to trigger 7.

Delays 9, 10, 12 and 13 are adjusted to apply the signals from trigger 7 to AND's 3 and 4 during the intervals between cl...