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Load Stabilized Esaki Diode Memory

IP.com Disclosure Number: IPCOM000097636D
Original Publication Date: 1961-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Lawrence, WW: AUTHOR [+2]

Abstract

The memory presents a constant load to word and bit drivers which simplifies the design of such drivers.

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Load Stabilized Esaki Diode Memory

The memory presents a constant load to word and bit drivers which simplifies the design of such drivers.

The memory comprises a plurality of storage cells connected in matrix form. The basic sell is shown enclosed in a dotted box, the cell comprising X(1), X (1)', Y(2) and Y(2)' lines which intersect to form subcrosspoints X(1)Y(2), X(1)Y(2)', X(1)'Y(2), and X(1)'Y(2)'. Tunnel diodes D1... D4 are connected between the lines of the respective sub-crosspoints. Each is adapted to switch stable conditions (0 to 1) when positive (+) and negative (-) half select pulses are applied to the associated X and Y lines. The D1 of each cell is the diode of logical interest. D2...D4 are provided for load stabilization purposes.

Drivers (not shown) are connected to all X and Y lines of the memory. The drivers are either triggers or double-ended drivers which provide outputs of either + and ground or ground and + to a selected pair of X and X' lines and either - and ground or ground and - to a selected pair of Y and Y' lines. The truth table (lower drawing) for a cell indicates that for any combination of input pulses one and only one diode switches in the cell. Accordingly, any combination of input pulses switches the same number of diodes on a line each time the pulses are applied. As an example, applying a - pulse and ground to the Y(2) and Y(2)' lines and a + pulse and ground to the X(1), X(2) and X(3) and X(1)', X(2)' and X(3)' lines, respe...