Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Analog-to-Digital Converter

IP.com Disclosure Number: IPCOM000097655D
Original Publication Date: 1961-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Taylor, RL: AUTHOR

Abstract

In an analog-to-digital converter, it is important to maintain a linear relationship between the applied input voltage and the digital value derived by the counter. To that end, a reversible counter 16 is employed to compensate for any frequency drifts which occur in the two oscillators 11 and 13 of the converter.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 69% of the total text.

Page 1 of 2

Analog-to-Digital Converter

In an analog-to-digital converter, it is important to maintain a linear relationship between the applied input voltage and the digital value derived by the counter. To that end, a reversible counter 16 is employed to compensate for any frequency drifts which occur in the two oscillators 11 and 13 of the converter.

An input voltage of unknown magnitude is applied to voltage switch 10. This voltage, when appearing at the output of 10, controls the frequency of 11, a voltage-responsive variable-frequency device. The output signal of 11 is mixed in a frequency converter 12 with the output 13, a fixed-frequency generator. The low-frequency components of the beat-frequency signal derived by 12 are selected by a low-pass filter 14 and are then shaped by shaper 15. The latter develops, for application to the reversible counter 16 through AND 17, a series of pulses. These have a repetition rate which is directly proportional to the magnitude of the input voltage applied to 11 by 10. The latter may have a fixed offset voltage.

An oscillator 18 supplies a train of pulses t(1) (lower drawing) to a two-stage binary counter 19 and to a control unit 20 which has three conventional triggers. The output circuits of 19 supply trains of timing pulses t(2) and t(3) to unit 20. The latter supplies control signals to AND 17, to counter 16 and to switch 10.

The frequency of the outputs 11 and 13 may undesirably vary with changes in operating conditions and o...