Browse Prior Art Database

High-Order-First Arithmetic Device

IP.com Disclosure Number: IPCOM000097677D
Original Publication Date: 1961-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 74K

Publishing Venue

IBM

Related People

Allen, FK: AUTHOR

Abstract

The circuitry performs qui-binary addition or subtraction by handling the high order digits first. The system utilizes a special 6-bit code which contains four numeric bits and two zone bits. The numeric bits 8, 4 and +-2 provide the quinary values 0, 2, 4, 6 and 8. The numeric bit I provides the binary values 0 and 1. The zone bits A and B are utilized either to encode alphabetic data or when performing addition to store the carries from the qui-binary adder.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 94% of the total text.

Page 1 of 2

High-Order-First Arithmetic Device

The circuitry performs qui-binary addition or subtraction by handling the high order digits first. The system utilizes a special 6-bit code which contains four numeric bits and two zone bits. The numeric bits 8, 4 and +-2 provide the quinary values 0, 2, 4, 6 and 8. The numeric bit I provides the binary values 0 and 1. The zone bits A and B are utilized either to encode alphabetic data or when performing addition to store the carries from the qui-binary adder.

All digits are added and the preliminary sums and carries are stored in a shift register 11. After all digits have been added, the carries (from digit to digit) are shifted forward one position within the A register so as to align with the next higher digit. The addition cycle is repeated using the digits as one input and the carries as the other input to the adder until no carries are generated. The arithmetic is qui-binary. It is therefore necessary to add the binary carries to the quinary sums without shifting from decimal to decimal. Carries from the quinary are shifted prior to adding to the binary portion of the next higher decimal position.

The shift controls for the A bit shift register provide the extra shift cycle. The circuit is used with a key-driven input which is inherently high order first. As the output device also operates from left to right, a fully compatible system is provided which requires no reverse scan and which permits the utilization of a unidire...