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Tree

IP.com Disclosure Number: IPCOM000097689D
Original Publication Date: 1961-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Earle, J: AUTHOR

Abstract

The complete logic tree is a decoder and starting point for minimization of decoder type circuits. A two input variable tree, e. g., provides four outputs which are terms of the standard sum of products. However, should the logical requirement be less than a complete decoder, certain unnecessary branches of the tree may be removed without loss of the required logic.

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Tree

The complete logic tree is a decoder and starting point for minimization of decoder type circuits.

A two input variable tree, e. g., provides four outputs which are terms of the standard sum of products. However, should the logical requirement be less than a complete decoder, certain unnecessary branches of the tree may be removed without loss of the required logic.

The inversion characteristics of the logical AND inverter (stroke function) circuit necessitate a special type of diamond configuration to form the logical equivalent of the tree. For n variables there are required logical banks 0... n of stroke blocks, each bank except banks 0 and n having a plurality of stroke blocks.

Inputs to the first bank stroke block are each of the input variables. Inputs to the second bank of stroke blocks are the outputs of the first bank stroke block and all possible combinations of one less than all input variables to the respective stroke circuits. Each stroke block in any (xth) bank is provided inputs from each of the preceding bank outputs and all possible combinations of (n-x) input variables. The nth bank stroke block is provided an input from each of the circuits in the preceding banks. The output of each stroke block is one term of the standard sum of products.

AND-inverter blocks 1, 2, 3 and 4 (upper drawing) provide outputs at respective nodes 1, 2, 3 and 4. The center drawing shows the detail of one block. The following signals are available directly at the nodes:

(1) bar AB (3) bar AB

(2) bar (A * bar B) (4) bar (bar A * bar B)

Combinations of outputs from two or more nodes wired as a bundle to a receiving block (not shown) indicate the following functions: (1, 4) bar A * bar B + AB (2, 3) A * bar B + AB

Minimization techniques can be performed to remove unnecessary portions of the configuration.

Blocks 11... 18...