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Checking Circuit

IP.com Disclosure Number: IPCOM000097723D
Original Publication Date: 1961-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Trampel, KM: AUTHOR

Abstract

The circuit is a 2 out of 5 validity checking circuit. As shown by the operational waveforms, this circuit samples the 5 input bits and provides an up output when two, and only two, of the input bits are down.

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Checking Circuit

The circuit is a 2 out of 5 validity checking circuit. As shown by the operational waveforms, this circuit samples the 5 input bits and provides an up output when two, and only two, of the input bits are down.

In the operation of this circuit, the input resistors R1's and the on bias resistor R2 are so chosen that T1 conducts whenever any four or more of the inputs are up (OV). In addition, these resistors are so selected that T1 cuts off whenever two or more inputs are down (-Vin).

The input resistors R3's and the on bias resistor R4 are so chosen that T2 conducts whenever two or less inputs are down (-Vin). In addition, these resistors are so selected that T2 cuts off whenever three or more inputs are down (-Vin).

The purpose of resistors R6 and R7 is to provide a voltage a few tenths more positive than the collector of T2 at the base of T3, when T2 is in conduction. Therefore, when both transistors T1 and T2 are in conduction, transistor T3 is cut off due to its base-emitter being reversely biased. This reverse bias is shown in Region 1 (delta Va). The output is down (-V3 or 1).

When T1 is cut off and T2 is in conduction, transistor T3 acts as an emitter follower and the emitter of T3 differs from its base by its Vb drop ( delta Vb). The output is clamped in its up state by the diode D1.

When both T1 and T2 are cut off, transistor T3 is cut off due to its base- emitter being reversely biased (V2 = V1 + delta Vc).

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