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Browse Prior Art Database

Latch With Positive Logic Reset

IP.com Disclosure Number: IPCOM000097727D
Original Publication Date: 1961-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Dietrich, RH: AUTHOR

Abstract

In this latch circuit a positive signal on the reset terminal 1 resets the latch regardless of the polarity of the signal applied to the set terminal 2. The waveforms represent the signals applied to the reset and set terminals 1 and 2, along with the resultant output waveform at terminal 3.

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Latch With Positive Logic Reset

In this latch circuit a positive signal on the reset terminal 1 resets the latch regardless of the polarity of the signal applied to the set terminal 2. The waveforms represent the signals applied to the reset and set terminals 1 and 2, along with the resultant output waveform at terminal 3.

At time T1, terminals 1 and 2 are negative, causing transistor 5 to conduct. The output of 5 is applied to transistor 6, causing it to conduct. The latch remains in this set condition until a positive reset pulse is applied on 1. Therefore, if a positive signal is applied to 2 at T2, the signal is conducted through line 7 to 6 preventing the latch from being reset.

At T3, a positive reset signal is applied to 5, causing it to stop conducting, which in turn causes 6 to stop conducting. The latch is placed in this reset condition even though, at T3, the signal on 2 is negative. The diode 8 isolates this negative signal from 5. The latch remains in the reset state until the positive reset signal is removed and the positive set signal on 2 is removed at T4.

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