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Multi-State Memory Cell

IP.com Disclosure Number: IPCOM000097732D
Original Publication Date: 1961-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Stapper, CH: AUTHOR

Abstract

The memory cell employs an n number of tunnel and backward diodes and has an n + 1 number of stable states.

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Multi-State Memory Cell

The memory cell employs an n number of tunnel and backward diodes and has an n + 1 number of stable states.

The cell has n tunnel diodes 20 connected in series-aiding relation and is biased from a current source 22. A D. C. load for the diodes 20 is established by connecting n number of backward diodes 24 and the secondary 28 of pulse transformer 26 across the diodes 20. Transformer 26 permits the cell to be triggered from primary windings 30 (bit) and 32 (word).

A load line 34 for tunnel diode curve 36 shows the intersections with curve 36 establishing operating points 0... n. Each operating point signifies a single stable state in which the cell can exist, the nth operating point being the n + 1th stable state. Selection of a state is obtained by applying positive voltage pulses to windings 30 and 32, which shift the load line to the right of the tunnel diode curve. A state is selected by the voltage pulses being of sufficient magnitude to move the load line far enough to the right to clear the tunnel diode curve peak ahead of the desired state. The dotted portion 34a shows the state of the load line for storing a 2. Release of the pulses does not alter the selected state of the cell.

Output signals from the cell appear on the bias line. The signals are quantized versions of the input pulses which render the present cell suitable for use as an analog to digital converter.

Reset of the cell is accomplished by applying a negative pulse to...