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Synchronizing Circuit

IP.com Disclosure Number: IPCOM000097750D
Original Publication Date: 1961-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Hsiao, MY: AUTHOR [+2]

Abstract

The circuit provides a start impulse on the line 4 if any one of three synchronizing characters is properly received.

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Synchronizing Circuit

The circuit provides a start impulse on the line 4 if any one of three synchronizing characters is properly received.

Characters are six bits long and the bits are received in a serial manner from line 5 by shift register 6. In this case it is desired to have a start impulse upon the arrival of bit 19 which represents significant data.

The synchronizing characters selected have a comma-free characteristic in that while shifting is in process no valid character will be recognized. In addition, a single bit in any of the six bit synchronizing characters can be transposed without affecting this comma free aspect.

If the first character is received properly, gate A1l and gate A2 set trigger T1. The output of T1 along with a clock pulse CP through gate A5 initiates counting in a three position binary counter which includes bistable triggers FF1, FF2 and FF3. Initially the counters FF1... FF3 and FF4...FF6 are reset to a count of 001 from lines 7 and 8. Six clock pulses CP through gate A5 result in an output from the counter FF1... FF3 on all lines 9... 11 to gate A6.

The counting of counter FF1... FF3 takes place during the interval of time when the second synchronizing character would ordinarily be received. The output of gate A6is directed to an OR 12 by line 13.

If the second synchronizing character is properly received during the second synchronizing interval, gates A1 and A3 are conditioned to set trigger T2 so that an output is also available at this time on li...