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Error Detection Circuits

IP.com Disclosure Number: IPCOM000097753D
Original Publication Date: 1961-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Brown, DT: AUTHOR [+2]

Abstract

Common circuitry at each end of a transmission line, together with a small amount of additional gating, is used for data conversion and error detection purposes.

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Error Detection Circuits

Common circuitry at each end of a transmission line, together with a small amount of additional gating, is used for data conversion and error detection purposes.

Characters or words are entered in parallel from a data source 1 over lines
2...5 into an encoder shift register 6. Bits from 6 are transmitted over the communication channel 7 for re-assembly in a decoder 8 at the receiving end of the line and for utilization by an output device 9.

The first word W1 of a message containing the words W1, W2...Wn is entered in 6 and transmitted directly to 8. Here it is read out to 9 and then re- entered for subsequent use. Word W1 is also re-entered in 6 and then word W2 is read into 6. This results in development of sum modulo two representations in each bit position. The sum modulo two character or function is then shifted over the line 7 and combined through an Exclusive-OR 10 with the word W1 in the decoder register 8. The result obtained in 8 is the word W2. Sum modulo two functions of each succeeding pair of words in the message are derived in the encoder in a similar manner, including the next to the last word, Wn-1, and the last word, Wn, which are combined to form the sum modulo two character Wn-1 XOR Wn. The last word of the message Wn is transmitted directly, and correct transmission is indicated by the presence of zeros in all bit positions of the decoder.

An interesting aspect of the detection scheme is that if an error occurs in the...