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Browse Prior Art Database

Configuration Displacement Error Check

IP.com Disclosure Number: IPCOM000097754D
Original Publication Date: 1961-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Delmege, JW: AUTHOR

Abstract

In data manipulation on a byte basis, i.e., a selected group of bits, in a high speed digital computer, each byte includes a parity bit, and a check circuit is provided to determine that the selected byte is being manipulated. This condition is indicated when one of control flip flops 1...4 is set in the 1 state and the remainder set in the 0 state. Assuming that flip flop 1 is set, the 1 and 0 outputs from flip flops 1 and 2 are applied directly through inverter circuits 6 and 7, respectively, to parity circuit 5.

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Configuration Displacement Error Check

In data manipulation on a byte basis, i.e., a selected group of bits, in a high speed digital computer, each byte includes a parity bit, and a check circuit is provided to determine that the selected byte is being manipulated. This condition is indicated when one of control flip flops 1...4 is set in the 1 state and the remainder set in the 0 state. Assuming that flip flop 1 is set, the 1 and 0 outputs from flip flops 1 and 2 are applied directly through inverter circuits 6 and 7, respectively, to parity circuit 5.

Parity circuit 5 is a switching circuit described on page 20 of the IBM Technical Disclosure Bulletin, Volume 3, No. 8, January 1961. P circuit 5, when pulsed, provides an output signal indicative of a unique condition of the conditioning 1 and 2 inputs. The outputs from flip flops 3 and 4 are similarly connected directly through inverters 8 and 9 to parity circuit 10. The inputs to the P circuits 5 and 10 are also applied to bar A circuits 11 and 12, the outputs of which are connected to gate circuits 13 and 14 respectively.

Under the assumed condition, gate 14 is conditioned and, when sampled by a pulse on line 15, applies a signal via line 16 to P circuit 5. The resulting output on line 17 sets flip flop 18 of a check register to the 1 state. Flip flop 19 remains in the 0 state under the assumed condition. Parity circuit 20 in response to a pulse on line 21 provides an output on line 22 indicative of the state...