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Resistor Diode Inverter Logic Circuit

IP.com Disclosure Number: IPCOM000097761D
Original Publication Date: 1961-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Antipov, I: AUTHOR

Abstract

The logical circuitry comprises a plurality of OR's 1...3 whose outputs are coupled to AND 4 for driving the base of transistor inverter 5. Each OR 1...3 includes a plurality of resistors R1, R2, R3 for accepting the various input signals. AND 4 comprises the diodes D1, D2, D3 and the resistor R5. If AND 4 is eliminated from the circuit so that the points indicated as A and B are joined, and, if only OR 1 is coupled to inverter 5, the circuit is a conventional NPN NOR logic block. Such a block is subject to oversaturation of the transistor due to the simultaneous switching caused by a change in level of the inputs to the OR block.

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Resistor Diode Inverter Logic Circuit

The logical circuitry comprises a plurality of OR's 1...3 whose outputs are coupled to AND 4 for driving the base of transistor inverter 5. Each OR 1...3 includes a plurality of resistors R1, R2, R3 for accepting the various input signals. AND 4 comprises the diodes D1, D2, D3 and the resistor R5. If AND 4 is eliminated from the circuit so that the points indicated as A and B are joined, and, if only OR 1 is coupled to inverter 5, the circuit is a conventional NPN NOR logic block. Such a block is subject to oversaturation of the transistor due to the simultaneous switching caused by a change in level of the inputs to the OR block.

When D1 and R5 are included in series with OR 1, a constant base current is supplied to the transistor irrespective of the number of inputs to the OR block. More specifically, when one of the inputs is at an up level, point A is more positive than B and the diode is reversely biased. If additional inputs go to an up- level, D1 is further reversely biased. Therefore, oversaturation of the transistor is eliminated, and the circuit provides an improvement in speed over the conventional NPN NOR logic.

In addition, by connecting D2 and D3 in parallel with D1 and by adding OR's 2 and 3 in series with their respective diodes, an additional logic decision is performed in essentially the same time as is normally required for a single decision. In effect, the delay per logic function is reduced by a factor of...