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Data Transfer Apparatus

IP.com Disclosure Number: IPCOM000097770D
Original Publication Date: 1961-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 50K

Publishing Venue

IBM

Related People

Adams, LR: AUTHOR [+2]

Abstract

A data transfer apparatus incorporates a number of interconnected magnetic core registers. A temporary or secondary storage element at the output of a stage of one register is capable of being selectively coupled to any one of the stages of the other registers.

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Data Transfer Apparatus

A data transfer apparatus incorporates a number of interconnected magnetic core registers. A temporary or secondary storage element at the output of a stage of one register is capable of being selectively coupled to any one of the stages of the other registers.

Each register has two stages and each stage includes a magnetic core such as 5 or 6. Information is fed into the register over input line 98 to winding 80 so as to switch core 5 to a set state. This information is read out from 5 to 6 by simultaneously energizing the shift or reset line 99 and a readout line 105. Negative potentials are applied to both lines 99 and 105. The negative potential from 105 is applied to winding 87 and to base 7 of transistor amplifier 29. This potential is insufficient to turn this transistor on. However, if core 5 is reset by the negative potential from line 99, a voltage is induced in the winding 87. Its magnitude is such that, together with the potential from line 105, the base of transistor 29 is lowered sufficiently to allow the latter to conduct and charge condenser 34. The bit of information originally stored in 5 is thus read out and switched by transistor 29 to condenser 34 and temporarily stored in the latter. If the serial readin control line 101 is energized by the application of a negative potential, the condenser 34 is discharged through winding 20 of core 6 and the latter is set to store the bit.

To regenerate the bit which is temporarily...