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IP.com Disclosure Number: IPCOM000097803D
Original Publication Date: 1961-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 63K

Publishing Venue

IBM

Related People

Hsiao, MY: AUTHOR

Abstract

The circuit translates six-bit codes into four-out-of-eight codes automatically. A unique configuration of four 1 bits and four 0 bits appears at the output for each combination of six bits applied to the input.

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Code Translator

The circuit translates six-bit codes into four-out-of-eight codes automatically. A unique configuration of four 1 bits and four 0 bits appears at the output for each combination of six bits applied to the input.

Characters in the six-bit code are serially applied to a 1's counter and to a serial to parallel converter. A six position clock controls the entry of input characters, each being entered at the rate of one bit per clock pulse CP. The clock resets the counter at CP6 time after each character entry cycle is completed. A logic circuit enabled at CP6 time indicates the number of 1 bits in each six bit input character.

An input character having four 1 bits is indicated at CP6 time by a signal on logic line 2V3V4. This enables circuits which transfer the input character to the output without change. Input characters having two or three 1 bits are indicated by signals on line 2V3V4 and either line 2 or line 3. These signals condition circuits to transfer the input character to the output without change and supply the proper number of additional bits to the output. There is a signal on the line bar 2V3V4 if the input character contains one, five or six 1 bits, this signal causing the necessary compensations to be performed by the circuits. An example of operation for an input character containing six 1 bits is shown. The progress of input character bits 1 and 0 through the circuit is indicated.

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