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Browse Prior Art Database

Distortion Error Detector

IP.com Disclosure Number: IPCOM000097804D
Original Publication Date: 1961-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Oeters, HR: AUTHOR

Abstract

The circuit determines if the duration of a signal pulse is within or without the tolerance limits for a single, double or larger number of integral pulse lengths.

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Distortion Error Detector

The circuit determines if the duration of a signal pulse is within or without the tolerance limits for a single, double or larger number of integral pulse lengths.

The signal on data line 1 is normally positive but may be made negative for an integral number of pulse durations to represent one or more signal pulses. A negative level change on 1 triggers a singleshot 2. A positive level change is passed through inverter 3 to trigger a second single shot 4. The positive pulses of 2 and 4 are combined in OR 5 to pulse a counter reset line 6 on each change of signal level. A counter 7 of any desired number of stages is driven by an oscillator 8. Its pulse rate is such that the counter is filled in one normal pulse interval. Thus, the counter 7 should return to a zero count at the end of any input pulse, since it is reset through line 6 to zero at the start of a pulse.

A counter decoder 9 is connected to the counter stages and functions to provide a positive output signal at all times when the input signal on line 1 should not rise to the positive level. The data signal on 1, the data change signal on 6 and the output of 9 are combined in AND 10 to indicate on line 11 that the termination of a signal on line 1 occurred outside of the tolerance limits for an integral number of pulse lengths. A delay 12 (dotted lines) may be inserted in line 6 to slow down the change in the output of counter 8 and thus extend the length of an error pulse on lin...