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Character Sequence Recognition Circuit

IP.com Disclosure Number: IPCOM000097805D
Original Publication Date: 1961-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Flautt, PW: AUTHOR

Abstract

The circuit including triggers T1... Tn provides a gating impulse on line 1 to an output device OD only if a predetermined sequence of characters X, Y and n is received from the decoder 2.

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Character Sequence Recognition Circuit

The circuit including triggers T1... Tn provides a gating impulse on line 1 to an output device OD only if a predetermined sequence of characters X, Y and n is received from the decoder 2.

In a typical case, characters are assembled in a shift register 3 after arriving bit by bit from a communication source at terminal 4. The shift register levels B...1 are applied by a cable 5 to the decoder 2. This supplies a single output pulse for each character from cable 6 to the sequence circuit and the output device OD. Each of the triggers T1... Tn is of the dual-gated type and includes an ON-1 and an OFF-0 block. Periodic shift impulses from a terminal 7 are applied to the ON and OFF blocks of all triggers by way of lines 8... 13. All positions are reset initially by a D. C. impulse from terminal 14 on lines 15, 16, and 17.

The output from decoder 2 for the character X applied to gates 1 and 2 on lines 18 and 19, in conjunction with the shift pulse on line 8, sets T1. In order to avoid a racing condition, a requirement of the circuit is that the gate inputs of any ON or OFF block be conditioned a certain amount of time prior to the arrival of a shift pulse, such as . 5 microseconds.

T1 being ON conditions gate 2 of T2 on line 20 and also conditions gates 3 and 4 of T1 on lines 21a and 21b for resetting purposes. The receipt of the character Y impulse on line 22 conditions gate 1 input of T2. A subsequently arriving shift pulse from terminal 7 sets T2 on line 10 and resets T1 on line 9.

The ON side output of T2 on line 23 conditions the gate 2 input of Tn and also conditions the gate 3 and 4 inputs of T2 on lines 24a and 24b. If the third character n is received as indicated by an impulse on line 25, the gate 1 input of Tn is conditioned. The next arriving shift pulse from terminal 7 sets Tn on line 12 and resets T2 on line 11. If only three characters are used for gati...