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Parallel BCD Adder

IP.com Disclosure Number: IPCOM000097806D
Original Publication Date: 1961-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 57K

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Parallel addition of binary coded decimal (BCD) numbers without carry propagation delays is accomplished.

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Parallel BCD Adder

Parallel addition of binary coded decimal (BCD) numbers without carry propagation delays is accomplished.

A number of BCD addend digits X1... X10 and a number of BCD augend digits Y1... Y10 are entered in parallel into both a bit carry generator BCG1... BCG10 and a digit adder DA1... DA10. Each digit adder position, i. e., DA1 generates the binary sum BS1 of the corresponding BCD input digits X1 and Y1. A bit carry generator BCG1 supplies all binary inter-bit carries required by the associated digit adder.

All the binary digit sums BS1... BS10 are simultaneously corrected to BCD sums in the decimal correction circuits DCC1... DCC11. These are active with respect to any particular BCD for instance BS1, sum when the sum is nine or more, as indicated by a signal on either line BS1=9 or line BS1? 9. All decimal digit carries C1... C10 are simultaneously generated in the digit carry generator DCG1... DCG10. This is when a digit is indicated as being more than nine BSn>9 or which is indicated as being nine (BSn=9) when the adjacent lower order digit is more than nine (BSn-1> 9).

All the corrected BCD sums are simultaneously adjusted in the carry insertion circuits CI1... CI11 to compensate for the digit carries C1...C11, resulting in a final output of parallel BCD sums S1...S11.


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