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A Two Transistor Ternary Inverter

IP.com Disclosure Number: IPCOM000097811D
Original Publication Date: 1961-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Trampel, KM: AUTHOR

Abstract

This inverter circuit inverts a signal residing in either one of two voltage levels and merely passes a third voltage level. The three voltage levels are GND, V2 and V3. The voltage level V2 is defined as N (nothing), located between a 0 and a 1. A ternary inverter circuit must invert the 0 and 1 levels and passes the N level.

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A Two Transistor Ternary Inverter

This inverter circuit inverts a signal residing in either one of two voltage levels and merely passes a third voltage level. The three voltage levels are GND, V2 and V3. The voltage level V2 is defined as N (nothing), located between a 0 and a 1. A ternary inverter circuit must invert the 0 and 1 levels and passes the N level.

The following table relates the input to its output for a ternary inverter: Input Output

0=V3 1 =GND

N=V2 N=V2

1=GND 0=V3

The operation of this circuit is as follows. The magnitudes of resistors R1 and R2 are such that transistor T2 conducts only when the input is a 0 (V3 volts) and is cut off when the input is either N or 1 (V2 or GND). Resistors R4 and R5 are so chosen that transistor T1 conducts when the input is an N (V2 volts) and is cut off when the input is a 1 (GND).

The circuit is so designed that when the input is a 0 (V3 volts), the collector base diode junction of transistor T1 is forwardly biased and is conducting. However, the base emitter junction of transistor T1 is reversely biased. The design of the circuit is such that the impedance of resistors R4 and R5 is high, and the current drain from the collector of transistor T2 is small compared to the available collector current from T2, i. e., the collector base current through T1 is small.

The right hand drawing indicates the circuit takes undefined input voltage levels, inverts them, and produces well defined output voltage levels.

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