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Delayed Single Shot

IP.com Disclosure Number: IPCOM000097814D
Original Publication Date: 1961-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Trampel, KM: AUTHOR

Abstract

The single shot circuit, after a well defined time delay, renders an output pulse having an accurately controlled width.

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Delayed Single Shot

The single shot circuit, after a well defined time delay, renders an output pulse having an accurately controlled width.

The circuit employs a delay line with a characteristic impedance Zo, a delay time Td, and an inductor L at the output. When transistor T1 is cut off, a voltage step occurs at its collector. The amplitude of the voltage step depends upon the resistors R3 and R4, the characteristic impedance Zo and the voltage supply -V5. The duration of the step is determined by the time the reflection takes to travel to the end of the delay line and back (2Td). Inductor L produces a reflection similar to an open delay line and drives the voltage at point B to V2. The voltage at B then decays to ground with a time constant L/(R3 + R4), which determines the output pulse width.

The operational waveforms show that when transistor T1 is cut off, due to the input voltage swing going positive, the potential at point B drops to -V1. After a time delay of 2Td transistor T2 is rendered conductive due to the potential at point B crossing (-V1 to -V2) the switching threshold of transistor T2. The potential at point B now decays with a time constant of L/(R3 +R4). T2 conducts until the decaying potential crosses the switching threshold. The pulse duration of T2 is adjusted by varying R5. Hence, the output pulse appearing at terminal C is delayed by a predetermined factor of 2Td and its width is controlled by the magnitude of resistor R5.

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