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Adder Circuit

IP.com Disclosure Number: IPCOM000097849D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 4 page(s) / 110K

Publishing Venue

IBM

Related People

Bedrij, OJ: AUTHOR

Abstract

In the adder circuit the delay time due to carry propagation is decreased to a minimum. The problem of carry propagation delay is overcome by dividing the digital positions of the addend and augend into a plurality of groups. Each group has a subaugend and a corresponding subaddend. During the first step in the operation, the subaugends and corresponding subaddends are simultaneously added twice to produce two subsums. One addition assumes that there is a carry into each group. The second addition assumes that there is no carry into each group. During the second step in the operation, the correct subsums for all groups are simultaneously selected.

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Adder Circuit

In the adder circuit the delay time due to carry propagation is decreased to a minimum. The problem of carry propagation delay is overcome by dividing the digital positions of the addend and augend into a plurality of groups. Each group has a subaugend and a corresponding subaddend. During the first step in the operation, the subaugends and corresponding subaddends are simultaneously added twice to produce two subsums. One addition assumes that there is a carry into each group. The second addition assumes that there is no carry into each group. During the second step in the operation, the correct subsums for all groups are simultaneously selected.

With the adder circuit a fifteen digit addend A1... A15 can be added to a fifteen digit augend B1... B15 to produce a fifteen digit true sum S1...S15. Provision is made for a carry input C(o) to the least significant digital position. This is the end around carry which is used for the addition of a negative number (represented in complement form) to a positive number. The fifteen digit augend and the fifteen digit addend are broken into three minor digital groups, a, b, and c, each group having a subaugend, a subaddend, and a true subsum of five digital positions.

The following numbering scheme is used. A sum symbol S or carry symbol C followed by y or n in the subscript, respectively, indicates a provisional digit which is generated under certain assumptions. A y indicates the presence and an n the absence of a carry into the lowest order digital position of the respective minor digital group under consideration. The absence of y or n is indicative for a true sum or true carry, respectively.

Each circuit 10 operates on five digital positions, e. g., the circuit 10a on the positions A1... A5 and B1... B5, and makes available two sums, e. g., S1y...S5y and S1n...S5n, as well as the carries, e. g., C5y and C5n. The circuits 10 are logical blocks connected according to the Boolean equations (1) through (12) which are given below for the circuit 10a. SEE ORIGINAL FOR FUNCTIONS p. 37-38 The logical design of the circuits 10b and 10c is basically the same as circuit 10a.

If the time required for one logical block to change state, after a signal is applied, is designated by T, the delay is 3T between acti...