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Address Translation

IP.com Disclosure Number: IPCOM000097850D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Blaauw, GA: AUTHOR [+2]

Abstract

Five byte addresses in a computer instruction are each treated as a blank byte, a symbolic block address byte, high order word address byte, low order word address byte, and byte address byte. During address translation, the symbolic block address byte is converted to a two byte actual block address. The actual block address replaces both the blank byte and the symbolic block address byte.

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Address Translation

Five byte addresses in a computer instruction are each treated as a blank byte, a symbolic block address byte, high order word address byte, low order word address byte, and byte address byte. During address translation, the symbolic block address byte is converted to a two byte actual block address. The actual block address replaces both the blank byte and the symbolic block address byte.

The instruction containing the symbolic block address is initially placed in the instruction register 2, which contains the blank, symbolic block, word, and byte addresses. A relocation control bit and a prefix address are entered in the program control word register 4. When the relocation control bit is 1, the symbolic block address byte is set into the memory address register MA via connections and gates A. The prefix fix address value is set into the high order positions of MA. Program rules call for the relocation table to be set into memory 6 locations (prefix) and (prefix + 1). MA is thus set to address a byte pair in the relocation table which contains the appropriate actual block address related to the symbolic address.

Connections and gates B read out the relocation table byte pair to the memory data register D. The byte pair is inspected for all 0's by the zero detector circuit. A zero entry indicates that the requested block address is not available and measures are taken to switch to a program for generating the requested block address. Connections and gates C then set the actual block address into the appropriate byte positions of register 2. Connections and gates A then transfer the entire register 2 content to MA to address the actual location desired.

During all processing, the address content of MA and the prefix are continuously monitored by the address monitor 8 to prevent relocation into a forbidden area of memory 6. In proper operation, the memory address must be greater than or equal to prefix plus two. Error mechanism is set off by monitor 8 when MA < (P + 2). The relocation table is thus protected.

EXAMPLE: The instruct...