Browse Prior Art Database

Precision Mode Bit

IP.com Disclosure Number: IPCOM000097851D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Hedrick, GB: AUTHOR [+3]

Abstract

Computers designed for scientific computation may use more than one floating point operand. In particular, single precision (half word) and double precision (full word) formats may be employed. Single precision yields high processing speed and large operand capacity. Double precision carries out computation to twice as many digital places as single precision.

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Precision Mode Bit

Computers designed for scientific computation may use more than one floating point operand. In particular, single precision (half word) and double precision (full word) formats may be employed. Single precision yields high processing speed and large operand capacity. Double precision carries out computation to twice as many digital places as single precision.

The choice of format is conveniently specified by a precision mode bit in the program control word of the computer. In both single and double precision modes, operands are normally stored adjacent to each other for effective utilization of memory. The expected consequence of such placement in storage is that operands need be addressed differently in the two modes, by full word or half word addresses. This difference involves not only absolute addresses but all address modification which is normally performed by increment operations or by fixed point arithmetic. Change from one mode to another can involve elaborate programs which anticipate all possible means of address computation. The function of the precision mode bit and its allied circuitry is to allow a program written in double precision mode to be used directly for single precision processing, without interference from address modification in its relationship with half word processing.

The computer normally addresses to the full word level by a binary coded address. In the drawing, double precision operands occupy full words at left in the memory. A block of (m+l) floating point operands lie in storage locations (N), (N+l)... (N+k)... (N+m).

Ek is the exponent and Fk is the fraction of the (k+l)th operand. Single precision operands occupy adjacent half-word locations >N/2|, ((N+2)/2|... ((N+k)/2|... l(N+m-2)/2|. The brackets ( | indicate the greatest integer the computer addresses only to the full word level. Choice of left or right half word is handled separately by a single underflow bit position; 0 is for left and 1 is for right half words.

Programs operate regardless of the precision of the data. To obtain the (k+l)th operand, the program specifies that the number k be added to a base address N to form a program address (N+k). Since in single-precision processing the desired effective address is ((N+k)/2|, value N is chosen, double the desired base address, so that after division by 2...