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Browse Prior Art Database

Indirect Addressing Arrangement

IP.com Disclosure Number: IPCOM000097853D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 69K

Publishing Venue

IBM

Related People

Jones, FB: AUTHOR

Abstract

During an instruction readout operation of the system, a twelve character instruction consisting of a two digit operation code and two five digit addresses are read out from twelve consecutive addresses of core memory 10. The address of the instruction is specified by a five digit instruction register 11. Its contents are transferred, parallel by bit and parallel-by-digit, to a memory address register 12 through gate unit 13 at the start of an instruction readout cycle. Each character has six binary bit positions, i.e., a check bit position, a flag bit position, and four BCD bit positions 8, 4, 2 and 1. Register 12 addresses 10 through memory addressing circuit 14 causing two digits to be transferred to an odd memory buffer register 15 and an even memory buffer register 16.

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Indirect Addressing Arrangement

During an instruction readout operation of the system, a twelve character instruction consisting of a two digit operation code and two five digit addresses are read out from twelve consecutive addresses of core memory 10. The address of the instruction is specified by a five digit instruction register 11.

Its contents are transferred, parallel by bit and parallel-by-digit, to a memory address register 12 through gate unit 13 at the start of an instruction readout cycle. Each character has six binary bit positions, i.e., a check bit position, a flag bit position, and four BCD bit positions 8, 4, 2 and 1. Register 12 addresses 10 through memory addressing circuit 14 causing two digits to be transferred to an odd memory buffer register 15 and an even memory buffer register
16. Depending on whether the units digit in 12 is odd or even, 14 causes one of the digits stored in the two consecutive addresses which are read out by 14 to be also transferred to a memory digit register 17. The two digits which are read out are returned to 10 by lines 19 and 20 during a memory regenerating cycle. The five digit address 12 is incremented by one or two address positions for each readout operation of 10 by means of the incrementing circuitry 21 and reentered into 11 through gate unit 22.

Readout of the twelve-digit instruction takes eight memory cycles and is under the control of eight instruction readout control triggers 1... 8. Trigger 1 functions to control the transfer of the two,digit operation code to operation register 22 through gate unit 23. Trigger 2 functions to control the transfer of the two high order digits P2-P3 of the P-field to the 10,000's and 1,000's positions of the P-field register 24 through a gate 25. Trigger 3 functions to control the transfer of the P4-P5 digits of the P-field to the 100's and 10's positions of 24through 25. Trigger 4 functions to control the transfer of the units digit P6 of the P-field to the units position of 24 through 25. Trigger 5 functions to control the transfer of the high order digit Q7 of the Q-field to the 10,000's position of the Q-field register 27 through gate 28. Trigger 6 functions to control the transfer of the Q8 and Q9 digits to the 1000's and 100's positions of 27 through 28. Trigger 7 functions to control the transfer of the low order digits Q10 and Q11 to the 10's and units positions of 27 through 28. Trigger 8 functions to control the entry of the computer into a cycle which allows the processor to perform the specific operation specified by the two-digit operation code 0001 in 23. This is decoded by decoder 29 and supplied to the program control execution means 31.

With a direct instruction, the P-field in 24 and the Q-field in 37 specify two specific addresses in memory which correspond to either the low-order or the high-order digits of the two data fields to be involved in execution of the instruction. If the P-field or the Q-field do not specify...