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Parallel Adder Error Checking System

IP.com Disclosure Number: IPCOM000097854D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Anderson, SF: AUTHOR

Abstract

Input signals are gated from registers A and B and applied in parallel to a high speed carry generator, of which the second denomination section only is shown. The signals are checked for gating errors by an input parity generator which determines the parity of the output from denominational EXCLUSIVE OR gate 1 and compares it in gate 2 with the parity bits from gate 3 for the A and B parity registers.

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Parallel Adder Error Checking System

Input signals are gated from registers A and B and applied in parallel to a high speed carry generator, of which the second denomination section only is shown. The signals are checked for gating errors by an input parity generator which determines the parity of the output from denominational EXCLUSIVE OR gate 1 and compares it in gate 2 with the parity bits from gate 3 for the A and B parity registers.

The high-speed carry generator, fed with the outputs of gate 1 and denominational AND 4, determines the carry from each denomination. These carries and the output from gate 1 are combined in gate 5 to generate sum signals for each denomination.

To check the generated carries and sums, the carry into an order, the checked output of gate 1 for that order and the checked A and B inputs are applied to two AND's 6 and 7. Their outputs are combined in OR 8 to generate an expected carry signal for the next higher order. The expected carry and the actual carry signals for a denomination are compared in gate 9 to energize a carry error line through gate 10, if a disagreement is detected.

The sum for a denomination is checked by applying an expected carry from the next lower denomination and the sum generated in the denomination to gate
11. The output from 11 and the output from gate 1 are compared in gate 12 to energize an input to OR 13 and generate a sum error signal, if any variation is sensed.

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