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Complementary Emitter Follower Storage Circuit

IP.com Disclosure Number: IPCOM000097867D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 33K

Publishing Venue

IBM

Related People

Walsh, JL: AUTHOR

Abstract

A circuit operating at low voltage levels and having a delay time from input to output of two nanoseconds employs the twin tunnel diode pair D1-D2 for bistable storage.

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Complementary Emitter Follower Storage Circuit

A circuit operating at low voltage levels and having a delay time from input to output of two nanoseconds employs the twin tunnel diode pair D1-D2 for bistable storage.

The solid line waveform shows the twin tunnel diode pair has a voltampere characteristic with two positive resistance regions. These are separated by a substantially linear negative resistance region. Complementary emitter followers T1 and T3 provide the load line (dashed line) for the diodes in conjunction with the transistors T2 and T4 which receive set and reset input signals.

In operation, when the input signal to T2 is at an up level and the input signal to T4 is at; down level, the output signal is at a down level or the low, voltage storage point (point 1). When the set input goes to an up level, the operating point transfers to the high voltage storage point (point 2). T1 is rendered non- conducting while T3 is rendered conducting. The input signal to T4 may now go to a down level and the circuit output signal remains at an up level, i. e., at point
2. The circuit is reset by applying a down level signal to T2. This causes the base electrode of T3 to be below ground level. The operating point then transfers from point 2 to point 1. The output signal drops from an up to a down level, causing T1 to conduct and T3 to be rendered nonconductive, completing a cycle of operation.

Depending on the characteristics of the transistors employed, it may be...