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Three-level Inverter Using A Two-emitter Transistor

IP.com Disclosure Number: IPCOM000097872D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+2]

Abstract

This circuit accepts a three level input signal and provides an inverted three level output signal. A two-emitter transistor, which is capable of conducting through either one or both of the emitters, is employed.

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Three-level Inverter Using A Two-emitter Transistor

This circuit accepts a three level input signal and provides an inverted three level output signal. A two-emitter transistor, which is capable of conducting through either one or both of the emitters, is employed.

The three level input signal VB is applied to input terminal 1.

When VB is below ground, conduction through the collector of transistor T1 is limited to the cutoff current as shown in the curve (IC vs. VB). When VB increases above ground, T1 begins conducting one unit of current through R1 and T2 ceases conduction. At this time the signal on output terminal 2 drops due to the potential drop across resistor R. When VB increases above the voltage value +V1, T1 begins conducting a second unit of current through R2 and transistor T3 ceases conduction. The output drops still further due to the increased current through R.

Since the units of current conducted by T1 are equal, the output signal on terminal 2 is symmetrical about a center value. The value of input voltage VB, for which T1 begins conducting each unit of current, is varied by varying the references applied to the bases of T2 and T3. The two-emitter transistor T1 can be replaced by two transistors with common base and collector terminals.

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