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Esaki Diode Latch Circuit

IP.com Disclosure Number: IPCOM000097873D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Dieffenderfer, J: AUTHOR

Abstract

This circuit employs two capacitor coupled Esaki diodes to realize a latch device.

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Esaki Diode Latch Circuit

This circuit employs two capacitor coupled Esaki diodes to realize a latch device.

The set state of the latch 10 is assumed as an initial condition for explaining circuit operation. In this state, Esaki diode D1 is in the high current state I max. and Esaki diode D2 is in the low current state I min. on the I-V curve 12. External manifestation of the set or reset state of latch 10 is provided by measurement of the current in either diode.

The reset signal is a positive current pulse Ir. When this current is present, the current in diode D2 reduces, switching it to a lower voltage state (defined by I max. when Ir returns to zero). Thus, the potential at node N2 goes more positive. Since capacitor C does not discharge instantaneously, a voltage pulse is propagated to node N1. Diode D1 switches to its low, current state I min. completing the reset.

The set signal is a negative current pulse Is. When this current is present, with latch 10 in the reset state, the current in diode D1 reduces switching it to a lower voltage state (defined by I max. when Is returns to zero). Thus, nodes N1 and N2 go more negative, D2 switches to the low current state I min., thereby establishing the set condition.

Should a set signal Is exist while the latch 10 is in set condition, or a reset signal In exist while the latch 10 is in the. reset condition, a noise signal is generated but the latch does not change its state. Should both a signal Is and reset signal...