Browse Prior Art Database

Load Sharing Decoding Switch For Direct Core Storage Addressing

IP.com Disclosure Number: IPCOM000097875D
Original Publication Date: 1961-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Guignabodet, JJ: AUTHOR

Abstract

The load-sharing decoding switch utilizes magnetic cores. Each core is provided with one input winding. Ten cores are used and the input windings are respectively 1...10. The output lines are threaded through the cores in definite winding patterns as indicated. Only a few of the one hundred total output lines utilized in one arrangement are shown. In operation, particular combinations of input lines are energized during a given period. Because of the distinct winding patterns of the output lines, the currents induced in the output lines add and/or subtract. One unique output line receives an output current larger than any of the other output lines.

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Load Sharing Decoding Switch For Direct Core Storage Addressing

The load-sharing decoding switch utilizes magnetic cores. Each core is provided with one input winding. Ten cores are used and the input windings are respectively 1...10. The output lines are threaded through the cores in definite winding patterns as indicated. Only a few of the one hundred total output lines utilized in one arrangement are shown. In operation, particular combinations of input lines are energized during a given period. Because of the distinct winding patterns of the output lines, the currents induced in the output lines add and/or subtract. One unique output line receives an output current larger than any of the other output lines.

A pair of the decoding switches can be used to provide coincident current selection in a core memory.

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