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Transistor Gain Tester

IP.com Disclosure Number: IPCOM000097905D
Original Publication Date: 1961-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Salisbury, DE: AUTHOR [+2]

Abstract

This circuit is a pulsed, dynamic current gain transistor tester. It automatically applies correct biasing and controls the turn on time of the transistor under test so that deleterious, capacitive effects caused by a too rapid turnon are avoided.

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Transistor Gain Tester

This circuit is a pulsed, dynamic current gain transistor tester. It automatically applies correct biasing and controls the turn on time of the transistor under test so that deleterious, capacitive effects caused by a too rapid turnon are avoided.

A positive pulse input is applied to the collector of transistor 1 and, through variable resistor 10, to the collector of transistor T20 being tested. Initially, there is no current flow through T20 due to the grounding of its base. In response to the positive input pulse, transistor 1 initiates a ramp voltage output at 9, which is applied to the base of transistor 3, gradually initiating conduction in it. A voltage is developed across resistor 6 that initiates conduction in transistor 4, which applies a ramp of current to the base of T20.

T20's collector potential falls as conduction is initiated in it by the increased base current. This negative going collector voltage is fed through diode 8 to the base of transistor 2 which conducts when its base goes negative with respect to its emitter. The emitter voltage of transistor 2 is set by reference potentiometer 7. This action turns on transistor 5 to decrease the base potential of transistor 4 and clamp the input base current to T20. The gain of T20 is then measured as the ratio of the collector current to the base current.

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