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Clock Recovery Or Rephaser Circuit

IP.com Disclosure Number: IPCOM000097933D
Original Publication Date: 1961-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Bagley, JD: AUTHOR

Abstract

Synchronization of clock signals is achieved at different locations by using signals on data input lines rather than separate synchronizing lines between the different clocks.

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Clock Recovery Or Rephaser Circuit

Synchronization of clock signals is achieved at different locations by using signals on data input lines rather than separate synchronizing lines between the different clocks.

Synchronization is effected between a master clock in a computer (not shown) and.a two-phase terminal clock 10 to provide logical Phase I and logical Phase II. The rephasing function is performed every nth character of data transmission.

Operation of the circuit starts when a Rephase Time pulse sets flip-flop FF1. An initial data bit occurs during Phase A, conditioning AND A1 and resetting flip-flop FF2. Resetting of FF2 conditions AND's A3 and A6, resulting in Phase A becoming logical Phase II and Phase B becoming logical Phase I. In the presence of logical Phase I, and a data bit on the input line, AND A7 is conditioned to produce a rephased data signal. To insure the rephased data lasts for the duration of Phase I, it is fed back to OR 03 to maintain A7 conditioned for the full length of logical Phase I.

This rephased data is also used to reset FF1 to prevent continued rephasing until the nth bit has been passed on the input data line, at which time the Rephase Time pulse once again initiates the rephasing cycle.

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