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Browse Prior Art Database

Asynchronous Multiplier

IP.com Disclosure Number: IPCOM000097935D
Original Publication Date: 1961-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Tilton, CJ: AUTHOR

Abstract

In a digital multiplier, the need for a clock, producing pulses for the control of the multiply operation, is eliminated. A control circuit provides each partial product with a cycle or period. This is of variable time duration, depending upon whether only a shift, or an add plus a shift operation, is required. A partial product entry is initiated without delay as soon as one partial product entry is completed.

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Asynchronous Multiplier

In a digital multiplier, the need for a clock, producing pulses for the control of the multiply operation, is eliminated. A control circuit provides each partial product with a cycle or period. This is of variable time duration, depending upon whether only a shift, or an add plus a shift operation, is required. A partial product entry is initiated without delay as soon as one partial product entry is completed.

The control circuit comprises OR 29, first closed loop including gate 25, long delay 22, OR 24, short delay 30 and gate 32. A second closed loop comprises gate 26, OR 24, short delay 30 and gate 32. A single control pulse, applied to OR 29, initiates a multiply operation. The end stage of the multiplier register is flip-flop 11. This receives, in sequence, each bit of the multiplier. If such a multiplier bit is 1, shift and add operations are necessary. If the bit is 0, only a shift operation is required. The control signals to initiate these operations are produced by the circuit.

The single control pulse, introduced through gate 29, is re-circled through the longer or shorter loop, depending on whether a 1,or 0 is in 16, and until terminated by de-conditioning the gate 32.

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