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Holding Circuit

IP.com Disclosure Number: IPCOM000097963D
Original Publication Date: 1961-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Prentky, PI: AUTHOR

Abstract

Analog systems require circuits for holding an output voltage at a predetermined level after a varying input voltage is changed or removed. The circuit provides a steady output voltage equal to the peak amplitude of an input pulse within a range of 0 to 2 volts.

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Holding Circuit

Analog systems require circuits for holding an output voltage at a predetermined level after a varying input voltage is changed or removed. The circuit provides a steady output voltage equal to the peak amplitude of an input pulse within a range of 0 to 2 volts.

The capacitor C is charged or discharged for each input pulse to develop a voltage equal to the peak amplitude of the input pulse. The voltage on C is applied to three emitter follower stages to develop an output equal to the voltage on C.

Transistors 1 and 2 form a feedback path from the output to C. The current which normally leaks off from C (at a rate determined by the initial charge) is exactly counteracted by transistors 1 and 2.

The proper relationship between feedback current, the voltage on C and at the output is determined by adjusting resistor 3. This provides the necessary current to the emitter followers to develop 0 volts at the output for 0 volts on C. Also, resistor 4 is adjusted to develop 2 volts at the output for 2 volts on C.

The remainder of the circuit, including Zener diodes 5 and 6 and transistors 7 and 8, provides regulation for power supply variations. The constant voltage drop across diodes 5 and 6 provides voltage references for 7 and 8. Thus, variations in the power supply cause 7 and 8 to produce compensating currents to maintain proper bias on transistors 1 and 2. Adverse effects, due to temperature, are reduced by using silicon transistors.

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