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End Carry Gate

IP.com Disclosure Number: IPCOM000097975D
Original Publication Date: 1961-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Schettl, MD: AUTHOR

Abstract

The circuit is a serial-plus-one adder with devices for determining when a maximum binary count is reached.

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End Carry Gate

The circuit is a serial-plus-one adder with devices for determining when a maximum binary count is reached.

Information delay line 10 circulates the binary count which is to be updated. Normally, a flip-flop 12, which is connected to a pair of AND's 14 and 16, is in a reset condition. This allows the binary count from line 10 to pass through 16 only, through a delay device 18, back to the line 10 in unchanged form. Updating is initiated by an impulse from a central timing source which sets flip-flop 12 conditioning AND 14 on and AND 16 off. The binary count is then passed through gate 14 to inverter circuit 20. If the binary count starts with a 0 bit, circuit 20 inverts the 0 bit to a 1 bit and applies this output to delay 10 and OR 22. OR 22 is connected to flip-flop 12 and the 1 bit applied to the OR is passed to reset flip-flop 12. With the reset of flip-flop 12, gate 14 is conditioned off and gate 16 is conditioned on. The remaining bits making up the binary count are then passed in similar form back to delay 10 through gate 16 and delay 18. Thus, if the original binary count is 100, then the first 0 bit is converted to a 1 bit, while the remaining bits are unchanged to provide an updated binary count of 101.

If the first bit of the binary count is a 1, with flip-flop 12 set, circuit 20 inverts this 1 bit to a 0 bit. The 0 bit is then applied to delay 10 without effecting a reset of flip-flop 12. All succeeding 1 bits are similarly converted un...