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Inverter With Override

IP.com Disclosure Number: IPCOM000097999D
Original Publication Date: 1961-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 40K

Publishing Venue

IBM

Related People

Bardell, PH: AUTHOR [+3]

Abstract

The latch circuit is responsive to first, second and third input signal levels and includes an override feature. The circuit has application in either ternary or asynchronous logical circuitry.

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Inverter With Override

The latch circuit is responsive to first, second and third input signal levels and includes an override feature. The circuit has application in either ternary or asynchronous logical circuitry.

The latch includes inverter circuit 10 having override provisions and diode logic block 12 for performing an AND operation, binary inverter 14 and diode OR
15. Inverter 10 has A and B inputs, the latter receiving first, second and third signal levels which correspond to positive, negative and ground input signals, respectively. The output of 10 is returned to AND 12 as one input. The other AND 12 input is from inverter 14. The AND 12 output is supplied as a OR 15 first input. Its second input is a reset signal at either a second or third level. The reset signal is also supplied to inverter 14. The OR 15 output is supplied to inverter 10 as the A input.

Inverter 10 (lower drawing) includes transistors 16, 18 and 20 connected at their collectors through resistors to supply +VS. Transistor 18 includes double emitters 19 and 21. Emitters of 16 and 20 connect to emitters 19 and 21, respectively, of transistor 18 through diode sets D1, D2 and D3, D4, respectively. Each set conducts current in both directions. Each emitter also connects through a resistor to supply -VS. A and B inputs are applied to the bases of 16 and 20. The base of 18 is grounded. The output for the inverter is taken at the collector of 18. With inputs A and B at ground, currents I1, I2, I3 and I4 flow through the emitters of 16, 18 and 20. As a result, D1, D2, D3 and D4 are non-conducting. The collector current of 18 is two units or the total of currents 12 and 13 through emitters 19 and 21. With B at third or ground level and A at first or positive level, D2 conducts the current 12. This turns off one emitter of 18 lowering the collector current from two units to one unit. When the A input is a second or negative level, D1 conducts the current I1 which shuts off 16. The collector current to 16 is diverted to 18, increasing its collector current from two units to three units. The one, two and three unit collector currents correspond to the first, third and second input levels. Thus, first and second inputs produce first and second output levels.

Applying a first or second level to 20 resets or overrides the output of 18 when the input to 16 is at a different level. A third or ground level input at 20 does not effect the output normally produced by the A signal alone. When the output is at a first or positive l...