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Three Level Inverter With Override

IP.com Disclosure Number: IPCOM000098000D
Original Publication Date: 1961-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 32K

Publishing Venue

IBM

Related People

Gruodis, AJ: AUTHOR

Abstract

This current switch is responsive to first, second and third level input signals to provide second, first and third output signals. The circuit is also adapted to receive an override signal at either a first or second or third level. The first and second override levels change the output signal to the second and first levels, when override and input are at different levels. When input and override are the same, the output is not effected by the override.

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Three Level Inverter With Override

This current switch is responsive to first, second and third level input signals to provide second, first and third output signals. The circuit is also adapted to receive an override signal at either a first or second or third level. The first and second override levels change the output signal to the second and first levels, when override and input are at different levels. When input and override are the same, the output is not effected by the override.

Each section of two is the mirror-image of the other. They connect to corresponding current sources which supply bias currents of magnitudes 21 and
I. One section responds to positive input signals, the other to negative input signals. Section one includes transistor T1 biased from the 21 source. The T1 emitter is clamped through diode D1 to reference voltage VR and connects to current sink 21. Transistor T2 is connected to receive a second signal. The T2 collector connects to current source I. The T2 emitter is clamped through diode D2 to VR and also connects to a current sink I. Common base amplifier T3 receives inputs through D5 and D6, respectively, the output currents from sources 21 and I. The T3 base is connected to +V. The T3 collector is connected through a resistor R to supply V. The output is taken across load resistor R.

Section two is identical except for the conductivity of the transistors T4, T5 and T6, the polarity of the current supplies 21 and I, and the connection of diodes D3, D4, D7 and D8 to the emitters of T4, T5 and T6. The two sections interconnect through an A input to T1 and T4, a B input to T2 and T5 and an output from the T3 and T6 collectors. The first, second and third level signals are termed positive, negative and ground signals, respectively. First and second levels applied to the B input are inverted at the output. First and second levels, applied to the A or override circuit, override the output signals to produce second and first levels, respectively, when the A and B signals are at different levels.

A ground input signal applied at A and B turns T1, T4 and T2, T5 on. This diverts the current from 21 and I, respectively, away from T3 and T6 to turn these off. With T1 and T4 being on, the emitters are clamped to associated reference voltages. Similarly, the T2 and T5 emitters are clamped to the reference voltage associated with them. Resistor R is chosen so that variations in the required output current, when ground signals are applied at...