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Three-Level, Non-Saturating Inverting Latch

IP.com Disclosure Number: IPCOM000098001D
Original Publication Date: 1961-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Gruodis, AJ: AUTHOR

Abstract

This circuit is a non-saturating inverting latch responsive to three different signal levels, namely, positive, ground and negative. The latch has two sections with transistors of opposite conductivity types. Section one responds to positive input signals. Section two responds to negative input signals. Section one has transistors T1 and T2 with their emitters connected together through diode D2 and each individually connected through resistors R1 and R2, respectively, to -V2. The T1 emitter also connects to reference potential -VR through diode D1. Input signals are supplied to the T1 base. The T1 and T2 collectors connect to supplies +V2 and +V1, respectively. Completing section one is an inverter including transistor T3 of conductivity opposite to T1 and T2.

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Three-Level, Non-Saturating Inverting Latch

This circuit is a non-saturating inverting latch responsive to three different signal levels, namely, positive, ground and negative. The latch has two sections with transistors of opposite conductivity types. Section one responds to positive input signals. Section two responds to negative input signals. Section one has transistors T1 and T2 with their emitters connected together through diode D2 and each individually connected through resistors R1 and R2, respectively, to - V2. The T1 emitter also connects to reference potential -VR through diode D1. Input signals are supplied to the T1 base. The T1 and T2 collectors connect to supplies +V2 and +V1, respectively. Completing section one is an inverter including transistor T3 of conductivity opposite to T1 and T2. The T3 collector is biased from voltage divider 10 including resistors R7 and R8 connected between supply +V5 and ground. The T3 collector also connects to the T2 base. The T3 emitter and base connect to the respective collectors of T1 and T2.

Section two includes transistors T4, T5 and T6 and diodes D3 and D4, all being connected in the same manner as the section one circuitry. Since the section two transistors are of opposite conductivity to those of section one, the supply polarities are reversed. The two sections interconnect through input circuit 40 which connects to the T1 and T2 bases. The T3 and T6 collectors are coupled to divider 10.

A reset circuit includes transistors T7 and T8 of opposite conductivity types, connected in inverter circuit configurations. The T7 emitter is clamped to reference voltage -VR through diode D6 and connects to supply +V2 through resistor R12. The T7 collector is connected through diode D5 to the T6 emitter. The T7 collector connects to the T8 base and to supply -V2 through resistor R9. The T8 emitter is clamped to supply -V1 through diode D7 which also connects through resistor R10 to the T7 collector. The T8 emitter connects to supply -V2 through R11. The reset circuit is completed by connecting the T8 collector to bias supply +V2 and resistor R3.

The output signal is provided at the T2 emitter and is positive, negative and ground for negative, positive and ground input signals, respectively. Switching of the circuit is rapid, since the voltage supplies and associated resistors are selected to provide currents that do not cause the transistors to saturate.

For a ground signal 20, the output signal is also ground signal 22 unless information is previously in the latch. Assuming that no information is in the latch, a ground signal causes T1 and T4 to be on. This provides sufficient current to retain T3 and T6, respectively, off. With both T3 and T6 off, the voltage at the T2 and T5 bases is that appearing at the node of divider 10. T2 and T5 are both turned on by the node voltage. T2 is an emitter follower so that the output voltage follows the signal at the base. The output voltage is adjust...