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Browse Prior Art Database

Storage Block Selection

IP.com Disclosure Number: IPCOM000098012D
Original Publication Date: 1961-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Cooper, TS: AUTHOR

Abstract

Two cores 11 and 13 (drawing A) are selectable by two X current diverters 15 and 17 and two Y current diverters 19 and 21. A diverter comprises a unilateral driver and an associated gate which gates current flow in a direction opposite to that which the driver provides. In the normal state, all diverters are on. To select core 11, diverters 17 and 21 are turned off. Half-select current flows from 17 to 15, and half select current flows from 21 to 19. Core 13 is uneffected, since the foregoing select currents cancel each other. Conversely, core 13 is selected by turning off 15 and 21.

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Storage Block Selection

Two cores 11 and 13 (drawing A) are selectable by two X current diverters 15 and 17 and two Y current diverters 19 and 21. A diverter comprises a unilateral driver and an associated gate which gates current flow in a direction opposite to that which the driver provides. In the normal state, all diverters are on. To select core 11, diverters 17 and 21 are turned off. Half-select current flows from 17 to 15, and half select current flows from 21 to 19. Core 13 is uneffected, since the foregoing select currents cancel each other. Conversely, core 13 is selected by turning off 15 and 21.

This is extended to a full storage core array (drawing B) in which the address sorter need address only 4K (4, 000) storage positions to select 8K positions. To select a core in either 4K(A) or 4K(B) planes, the associated diverters are controlled the same as in the basic circuit. The gates 23, 24, 25 and 26 provide line selection by an addresser.

To further expand to 16K positions, a total of four 4K groups or cores is used (drawing C). The gating scheme is the same as in B. Only one line is shown connecting the gates to the matrices. Phase reversal planes 30 and 31 provide for changing the relative direction in which the drive currents flow through the planes of adjacent matrices. The inhibit lines indicate that the same line controls both matrices A and B' and another line controls both matrices A' and B. Since in the Y dimension the addresser selects equiv...